Semiconductor structures and methods of manufacturing the same
US8604564B2 · kind B2 · utility
2Cited by
12References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2012 |
| Grant date | Dec 10, 2013 |
| Priority date | — |
| Expiry date | Mar 16, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure has embedded stressor material for enhanced transistor performance. The method of forming the semiconductor structure includes etching an undercut in a substrate material under one or more gate structures while protecting an implant with a liner material. The method further includes removing the liner material on a side of the implant and depositing stressor material in the undercut under the one or more gate structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.