Structure and method for reducing vertical crack propagation

US8604618B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Edward C. Cooney, III · Jericho, US
• Jeffrey P. Gambino · Gresham, US
• Zhong-Xiang He · South Burlington, US
• Xiao Hu Liu · Briarcliff Manor, US
• Thomas L. McDevitt · Underhill, US
• Gary L. Milo · Colchester, US
• William J. Murphy · North Ferrisburgh, US

Key dates

• Filing date: Sep 22, 2011
• Grant date: Dec 10, 2013
• Expiry date: Sep 22, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric insulator portion, a second metal conductor embedded within the second dielectric insulator portion, and a second nitride cap covering the second metal conductor. The first and second metal conductors form first vertically stacked conductor layers and second vertically stacked conductor layers. The first vertically stacked conductor layers are proximate the second vertically stacked conductor layers, and at least one air gap is positioned between the first vertically stacked conductor layers and the second vertically stacked conductor layers. An upper semiconductor layer covers the first vertically stacked conductor layers, the air gap and the second plurality of vertically stacked conductor layers.