Non-volatile SRAM cell that incorporates phase-change memory into a CMOS process
US8605490B2 · kind B2 · utility
23Cited by
4References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 12, 2009 |
| Grant date | Dec 10, 2013 |
| Priority date | — |
| Expiry date | Mar 15, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A SRAM cell having two cross-coupled inverters formed by CMOS technology and first and second chalcogenic elements integrated with the SRAM cell to add nonvolatile properties to the storage cell. The PCM resistors are programmed to the SET state and the RESET state, and upon power-up the SRAM cell takes on the data contained in the PCM cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.