Cache hierarchy with bounds on levels accessed
US8606997B2 · kind B2 · utility
8Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2008 |
| Grant date | Dec 10, 2013 |
| Priority date | — |
| Expiry date | Apr 28, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0862
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to a system managing data in a multilevel cache memory system. Certain cache data is designated and stored only in particular levels of the multilevel cache, bypassing other levels of the multilevel cache. In a multiprocessor environment, the present invention includes cache coherency operations or messages that pertain to data stored only in certain levels of a multilevel cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.