Transistor with embedded Si/Ge material having reduced offset and superior uniformity

US8609498B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Stephan Kronholz · Dresden, DE
• Peter Javorka · Radebeul, DE
• Roman Boschke · Dresden, DE

Key dates

• Filing date: Jan 13, 2011
• Grant date: Dec 17, 2013
• Expiry date: Aug 24, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0212

Abstract

In sophisticated semiconductor devices, a strain-inducing embedded semiconductor alloy may be provided on the basis of a crystallographically anisotropic etch process and a self-limiting deposition process, wherein transistors which may not require an embedded strain-inducing semiconductor alloy may remain non-masked, thereby providing superior uniformity with respect to overall transistor configuration. Consequently, superior strain conditions may be achieved in one type of transistor, while generally reduced variations in transistor characteristics may be obtained for any type of transistors.