Estimating power consumption of an electronic circuit

US8612911B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Thomas Buechner · Rabenau, DE
• Markus Buehler · Holzgerlingen, DE
• Philipp Panitz · Eppelheim, DE
• Lei Wang · Hangzhou City, CN
• Markus Olbrich · Langenhagen, DE

Key dates

• Filing date: Feb 3, 2012
• Grant date: Dec 17, 2013
• Expiry date: Feb 3, 2032

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2119/12
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method comprises estimating power consumption of an electronic circuit. The estimating includes assigning a first gate of the at least one gate into a priority queue based on a levelized result of the electronic circuit for a full circuit calculation and assigning a second gate of the at least one gate into the priority queue which fan-out gate is directly connected to a fan-in gate of a resized gate for an incremental circuit calculation. The estimating includes, for each gate from the priority queue, performing the following operations. Latest and earliest signal arrival times at an output net of the gate are determined by static timing analysis and calculating a glitch window as difference, and a transition metric is calculated for the output net based on the glitch window. The operations include determining an upper bound of signal transitions, and estimating the power consumption based on the upper bound.