Method of making a three-dimensional memory array with etch stop
US8614126B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2012 |
| Grant date | Dec 24, 2013 |
| Priority date | — |
| Expiry date | Aug 15, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/689
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three dimensional memory device including a substrate and a semiconductor channel. At least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of the substrate. The device also includes at least one charge storage region located adjacent to semiconductor channel and a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level. The device also includes an etch stop layer located between the substrate and the plurality of control gate electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.