Method and apparatus for logic read in flash memory
US8614920B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2012 |
| Grant date | Dec 24, 2013 |
| Priority date | — |
| Expiry date | Jun 17, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The timing of logic read operations in a Flash memory device may be improved by a pad serial output circuit which receives a pre-decoded instruction signal and pre-fetched logic data prior to the last command clock, and which performs a fast resolution of the command in the pad serial output circuit on the last clock of the command input sequence. In one illustratively implementation, instruction pre-decode and data pre-fetch may be done on the seventh clock during command input. In another illustrative implementation, a first instruction pre-decode and data pre-fetch may be done on the fourth clock during command input, and a second instruction pre-decode may be done on the seventh clock during command input. Both serial protocol interface, including dual and quad I/O SPI, and quad peripheral interface are supported.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.