Post-gate isolation area formation for fin field effect transistor device
US8617961B1 · kind B1 · utility
11Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2012 |
| Grant date | Dec 31, 2013 |
| Priority date | — |
| Expiry date | Jul 18, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fin field effect transistor (finFET) device formation includes forming a plurality of fins on a substrate; forming a gate region over the plurality of fins; and forming isolation areas for the finFET device after formation of the gate region, wherein forming the isolation areas for the finFET device comprises performing one of oxidation or removal of a subset of the plurality of fins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.