Through hole via filling using electroless plating
US8617987B2 · kind B2 · utility
6Cited by
2References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2010 |
| Grant date | Dec 31, 2013 |
| Priority date | — |
| Expiry date | Oct 8, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embedded wafer level ball grid array (eWLB) is formed by embedding a semiconductor die in a molding compound. A trench is formed in the molding compound with a laser drill. A first layer of copper is deposited on the sidewall of the trench by physical vapor deposition. A second layer of copper is then formed on the first layer of copper by an electroless process. A third layer of copper is then formed on the second layer by electroplating.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.