Semiconductor package using through-electrodes having voids
US8618637B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2008 |
| Grant date | Dec 31, 2013 |
| Priority date | — |
| Expiry date | Jan 26, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a semiconductor chip having a plurality of bonding pads. Through-electrodes are formed in the semiconductor chip and are electrically connected to the bonding pads. The through electrodes comprise a plurality of conductors and a plurality of voids that are defined by the conductors. Each conductor may include a plurality of nanowires grouped into a spherical shape having a plurality of voids, a plurality of nanowires grouped into a polygonal shape having a plurality of voids, or the conductors may include a plurality of micro solder balls. The voids of the through electrode absorb stress caused when head is generated during the driving of the semiconductor package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.