Progressive circuit evaluation for circuit optimization
US8621408B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2012 |
| Grant date | Dec 31, 2013 |
| Priority date | — |
| Expiry date | Apr 3, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and techniques for optimizing a circuit design are described. Some embodiments reduce the number of gates in the library (e.g., by dynamically pruning the library) which are considered for optimization. Some embodiments create a linear delay model, and use the linear delay model instead of a non-linear delay model to substantially reduce the amount of computation required to check whether or not a particular replacement gate improves one or more metrics of the circuit design. Some embodiments determine an order for processing the gates in the library or for processing input pins of a gate to facilitate early rejection of a candidate gate in the library of gates. In some embodiments, the evaluation of the impact of a candidate gate transformation is done progressively and level-by-level only up to the point where the gate transformation degrades one or more metrics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.