Method for fabricating semiconductor device with buried gate
US8623727B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2011 |
| Grant date | Jan 7, 2014 |
| Priority date | — |
| Expiry date | Jan 19, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate, forming an isolation layer for defining an active region by using the hard mask pattern, forming a buried gate in and across the active region and the isolation layer over the substrate, forming an inter-layer dielectric layer over the substrate, forming a storage node contact hole that exposes the hard mask pattern by selectively etching the inter-layer dielectric layer, extending the storage node contact hole to expose the active region by removing the hard mask pattern exposed under the storage node contact hole, and forming a storage node contact plug that fills the extended storage node contact hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.