Duty cycle correction circuit for memory interfaces in integrated circuits
US8624647B2 · kind B2 · utility
7Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2010 |
| Grant date | Jan 7, 2014 |
| Priority date | — |
| Expiry date | Nov 14, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00019
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuits and a method for correcting duty cycle distortions in an integrated circuit (IC) are disclosed. The IC includes a splitter circuit that is coupled to receive a clock signal. The clock signal is split into two different clock signals. One of the clock signals is an inverted version of the other. A delay circuit is coupled to each of the clock signals. Each of the delay circuits generates a delayed version of the corresponding clock signal. A corrector circuit is coupled to receive both the delayed versions of the clock signals. The corrector circuit generates a clock output signal with a corrected duty cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.