Multi-cell per memory-bit circuit and method
US8625339B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 11, 2011 |
| Grant date | Jan 7, 2014 |
| Priority date | — |
| Expiry date | Mar 7, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A write circuit is adapted to provide a same logical bit to each of a multitude of memory cells for storage. Each of the multitude of memory cells stores either the bit or a complement of the bit in response to the write circuit. A read circuit is adapted to receive the bits stored in the multitude of memory cells and to generate an output value defined by the stored bits in accordance with a predefined rule. The predefined rule may be characterized by a statistical mode of the bits stored in the plurality of memory cells. Storage errors in a minority of the multitude of memory cells may be ignored at the cost of lower memory density. The predefined rule may be characterized by a first weight assigned to bits 1 and a second weight assigned to bits 0.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.