Vertical SOI bipolar junction transistor and manufacturing method thereof

US8629029B2 · kind B2 · utility

Assignee

• SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY CHINESE ACADEMY OF SCIENCES · CN

Inventors

• Jing Chen · Shanghai, CN
• Jiexin Luo · Shanghai, CN
• Qingqing Wu · Shanghai, CN
• Jianhua Zhou · Campbell, US
• Xiaolu Huang · Shanghai, CN
• Xi Wang · Shanghai, CN

Key dates

• Filing date: Jul 14, 2010
• Grant date: Jan 14, 2014
• Expiry date: Aug 3, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D10/041

Abstract

The present invention discloses a vertical SOI bipolar junction transistor and a manufacturing method thereof. The bipolar junction transistor includes an SOI substrate from down to up including a body region, a buried oxide layer and a top silicon film; an active region located in the top silicon film formed by STI process; a collector region located in the active region deep close to the buried oxide layer formed by ion implantation; a base region located in the active region deep close to the top silicon film formed by ion implantation; an emitter and a base electrode both located over the base region; a side-wall spacer located around the emitter and the base electrode. The present invention utilizing a simple double poly silicon technology not only can improve the performance of the transistor, but also can reduce the area of the active region in order to increase the integration density. Furthermore, the present invention utilizes side-wall spacer process to improve the compatibility of SOI BJT and SOI CMOS, which simplifies the SOI BiCMOS process and thus reduce the cost.