Circuits and methods for providing refresh addresses and alternate refresh addresses to be refreshed
US8630141B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 28, 2011 |
| Grant date | Jan 14, 2014 |
| Priority date | — |
| Expiry date | Jul 17, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/408
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuits and refresh address circuits for providing a refresh address, and methods for refreshing memory cells. One such method includes refreshing a first plurality of memory cells and interrupting the refreshing of the first plurality of memory cells. A second plurality of memory cells is refreshed, at least one of the second plurality of memory cells the same as one of the first plurality of memory cells. Refreshing of the first plurality of memory cells is resumed following the refreshing of the second plurality of memory cells. One such refresh address circuit includes a refresh address counter configured to provide addresses to be refreshed and a refresh address interrupt circuit configured to interrupt the provision of addresses. An alternate refresh address circuit is configured to provide an alternate address and the refresh address counter resumes providing the addresses responsive to completing the refreshing of the alternate address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.