Processor and method of determining a normalization count
US8631056B2 · kind B2 · utility
3Cited by
9References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2008 |
| Grant date | Jan 14, 2014 |
| Priority date | — |
| Expiry date | Oct 13, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49936
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a particular embodiment, a method is disclosed that includes receiving an operand to be normalized at a normalization logic circuit, where the operand includes a plurality of bits. The method further includes generating a zero output when a value of the operand is equal to zero and, when the value is not equal to zero, generating an output value representing a number that is one less than a count of leading bits of the operand.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.