Patent · US Active

Method and system for generating a placement layout of a VLSI circuit design

US8631376B2 · kind B2 · utility

1Cited by

3References

14Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Tobias Werner · Holzgerlingen, DE
Anthony Parent · South Burlington, US
Raphael Polig · Dietikon, CH
Alexander Woerner · Eppelheim, DE

Key dates

Filing date	Jan 3, 2012
Grant date	Jan 14, 2014
Priority date	—
Expiry date	Jan 3, 2032

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/392
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method and a system for generating a placement layout is disclosed. The method includes receiving one or more user provided schematic with circuit data, placement parameters of circuit elements, default values, and user specified function calls and variables for calculating placement parameters; evaluating variables and function calls to discrete placement parameters; evaluating justification values and adjusting relative parameter values; calculating absolute placement coordinates for all cells from relative placement parameters for each instance; adjusting placement coordinates for alignment options; and generating a layout/hierarchical layout with placement circuit elements based on the calculated absolute placement coordinates.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.