Dynamic memory cell provided with a field-effect transistor having zero swing
US8634229B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 22, 2012 |
| Grant date | Jan 21, 2014 |
| Priority date | — |
| Expiry date | Oct 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
A memory cell is provided with a transistor which includes source and drain electrodes formed in a semiconductor film by respectively N-doped and P-doped areas. The transistor includes first and second devices for generating a potential barrier in the semiconductor film. The two potential barriers are shifted laterally and are opposed to the passage of the charge carriers emitted by the nearest source/drain electrode. One of the devices for generating the potential barrier is electrically connected to the gate. The other of the devices for generating the potential barrier is electrically connected to the counter-electrode. The writing of a high state is carried out by imposing on the P-doped electrode a potential higher than that of the N-doped electrode and charging the capacitor formed between the gate and the semiconductor film. The resetting of the memory cell is obtained by discharging the capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.