Integrated post-exposure bake track
US8636458B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2007 |
| Grant date | Jan 28, 2014 |
| Priority date | — |
| Expiry date | Jun 20, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/67109
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Systems and methods for processing wafers, a combined post expose bake and chill unit, and an interface are disclosed. An exemplary system includes a lithography tool, local track, transfer device, transfer device handler, interface unit, and controller to schedule processing. An exemplary combined post expose bake and chill unit includes an enclosure having an opening in its side, and a bake unit and a chill unit in the enclosure. An exemplary interface includes a plurality of enclosures arranged around robot(s) that transfer wafers among the enclosures, one of the plurality of enclosures being an integrated bake and chill unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.