Methods for fabricating a FINFET integrated circuit on a bulk silicon substrate

US8637372B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Yanxiang Liu · San Diego, US
• Xiaodong Yang · New York, US
• Jinping Liu · Ballston Lake, US

Key dates

• Filing date: Jun 29, 2011
• Grant date: Jan 28, 2014
• Expiry date: Jun 1, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/62
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods are provided for fabricating a FINFET integrated circuit that includes epitaxially growing a first silicon germanium layer and a second silicon layer overlying a silicon substrate. The second silicon layer is etched to form a silicon fin using the first silicon germanium layer as an etch stop. The first silicon germanium layer underlying the fin is removed to form a void underlying the fin and the void is filled with an insulating material. A gate structure is then formed overlying the fin.