3D integrated circuit system with connecting via structure and method for forming the same
US8637993B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2012 |
| Grant date | Jan 28, 2014 |
| Priority date | — |
| Expiry date | Apr 23, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an integrated circuit device includes providing a substrate including an active device, forming a through silicon via into the substrate, forming a device contact to the active device, forming a conductive layer over the through silicon via and the device contact, and forming a connecting via structure for electrically connecting the conductive layer with the through silicon via. An integrated circuit device includes a through silicon via formed into a substrate silicon material, a conductive layer formed over the through silicon via, and a connecting via structure formed between the conductive layer and the through silicon via for electrically connecting the conductive layer with the through silicon via. The connecting via structure comprises a first series of via bars intersected with a second series of via bars.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.