Inventor · Ballston Lake, NY, US

Chun Yu Wong

21Patents
4h-index
42Co-inventors
55Inventor score

Filing activity: Apr 23, 2012 → Oct 9, 2019

Most-cited inventions

PatentTitleAreaCited byStatus
US10475791B1 Transistor fins with different thickness gate dielectric Electricity 7 Active
US8637993B2 3D integrated circuit system with connecting via structure and method for forming the same Electricity 6 Active
US9706832B2 Dispensers and applicator heads therefor Human Necessities 5 Active
US9508795B2 Methods of fabricating nanowire structures Electricity 4 Active
US10418285B1 Fin field-effect transistor (FinFET) and method of production thereof Electricity 3 Active
US10804199B2 Self-aligned chamferless interconnect structures of semiconductor devices Electricity 2 Active
US9245790B2 Integrated circuits and methods of forming the same with multiple embedded interconnect connection to same through-semiconductor via Electricity 2 Active
US11018221B2 Air gap regions of a semiconductor device Electricity 1 Active
US10510662B2 Vertically oriented metal silicide containing e-fuse device and methods of making same Electricity 1 Active
US9601428B2 Semiconductor fuses with nanowire fuse links and fabrication methods thereof Electricity 1 Active
US10332834B2 Semiconductor fuses with nanowire fuse links and fabrication methods thereof Electricity 0 Active
US10879171B2 Vertically oriented metal silicide containing e-fuse device Electricity 0 Active
US9761481B2 Integrated circuits and methods of forming the same with metal layer connection to through-semiconductor via Electricity 0 Active
US10910276B1 STI structure with liner along lower portion of longitudinal sides of active region, and related FET and method Electricity 0 Active
US10461029B2 Hybrid material electrically programmable fuse and methods of forming Electricity 0 Active
US10439026B2 Fins with single diffusion break facet improvement using epitaxial insulator Electricity 0 Active
US10468481B2 Self-aligned single diffusion break isolation with reduction of strain loss Electricity 0 Active
US10043764B2 Through silicon via device having low stress, thin film gaps and methods for forming the same Electricity 0 Active
US9455188B2 Through silicon via device having low stress, thin film gaps and methods for forming the same Electricity 0 Active
US11171036B2 Preventing dielectric void over trench isolation region Electricity 0 Active
US10636894B2 Fin-type transistors with spacers on the gates Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.