Memory architectures and techniques to enhance throughput for cross-point arrays
US8638584B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2010 |
| Grant date | Jan 28, 2014 |
| Priority date | — |
| Expiry date | Oct 24, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement memory architectures configured to enhance throughput for cross point arrays including memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes arrays that include memory elements being formed BEOL above a FEOL logic layer within a boundary in a plane parallel to a substrate, and array lines. Further, the integrated circuit includes array line decoders disposed in the logic layer within a region located coextensive with the boundary and between the substrate and the arrays. In some embodiments, the disposition of peripheral circuitry, such as the array line decoders, under the arrays can preserve or optimize die efficiency for throughput enhancement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.