Partial local self boosting for NAND
US8638609B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2010 |
| Grant date | Jan 28, 2014 |
| Priority date | — |
| Expiry date | Jul 17, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system is programmed with minimal program disturb and reduced junction and channel leakage during self-boosting. Pre-charging bias signals are applied to word lines adjacent to a selected word line before a program signal is applied to the selected word line and a pass signal is applied to the remaining word lines. The pre-charging bias signals apply a pre-charge to the memory cells. The pre-charging bias signals are chosen to improve the isolation of the memory cells on word lines adjacent to the selected word line, improve self boost efficiency and reduce current leakage to prevent or reduce program disturb and/or programming errors especially in the inhibited memory cells on the selected word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.