Decoder for NAND memory
US8638618B2 · kind B2 · utility
4Cited by
1References
20Claims
0Family size
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Key dates
| Filing date | Jul 19, 2011 |
| Grant date | Jan 28, 2014 |
| Priority date | — |
| Expiry date | Jan 4, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device has multiple blocks of NAND memory cells, and a high voltage switch. The high voltage switch is coupled to a decoder output and the blocks of NAND memory cells. The high voltage switch has an output voltage range with positive and negative voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.