Early design cycle optimzation
US8640075B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2012 |
| Grant date | Jan 28, 2014 |
| Priority date | — |
| Expiry date | Jun 1, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.