Wafer level package structure and the fabrication method thereof
US8642385B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2011 |
| Grant date | Feb 4, 2014 |
| Priority date | — |
| Expiry date | Jan 14, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention proposes a package for semiconductor device and the fabrication method for integrally encapsulating a whole semiconductor chip within a molding compound. In the semicondcutor device package, bonding pads distributed on the top of the chip are redistributed into an array of redistributed bonding pads located in an dielectric layer by utilizing the redistribution technique. The electrodes or signal terminals on the top of the semiconductor chip are connected to an electrode metal segment on the bottom of the chip by conductive materials filled in through holes formed in a silicon substrate of a semiconductor wafer. Furthermore, the top molding portion and the bottom molding portion seal the semiconductor chip completely, thus providing optimum mechanical and electrical protections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.