Patent · US Active

Methods of forming isolation structures for semiconductor devices

US8642419B2 · kind B2 · utility

2Cited by

3References

9Claims

0Family size

Assignee

GlobalFoundries Inc. · KY

Inventors

Stephan Kronholz · Dresden, DE
Jorg Radecker · Dresden, DE
Hans-Juergen Thees · Dresden, DE
Peter Javorka · Radebeul, DE

Key dates

Filing date	Feb 20, 2012
Grant date	Feb 4, 2014
Priority date	—
Expiry date	Feb 20, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH01L21/76232
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Disclosed herein are various methods of forming isolation structures, such as trench isolation structures, for semiconductor devices. In one example, the method includes forming a trench in a semiconducting substrate, forming a lower isolation structure in the trench, wherein the lower isolation structure has an upper surface that is below an upper surface of the substrate, and forming an upper isolation structure above the lower isolation structure, wherein a portion of the upper isolation structure is positioned within the trench.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.