Thickened sidewall dielectric for memory cell
US8643082B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2011 |
| Grant date | Feb 4, 2014 |
| Priority date | — |
| Expiry date | Dec 29, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.