Apparatus and methods for altering the timing of a clock signal
US8643418B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2011 |
| Grant date | Feb 4, 2014 |
| Priority date | — |
| Expiry date | Oct 19, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00369
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Clock signal timing cells, clock signal timing circuits, clock circuits, memory devices, systems, and method for altering the timing of a clock signal are disclosed. An example method for altering the timing of an output signal provided responsive to an input clock signal includes adjusting a transition of an edge of the output signal from one voltage level to another based at least in part on a bias signal. An example clock signal timing cell includes an inverter and a bias controlled inverter coupled in parallel to the inverter. The bias controlled circuit is configured to provide an output signal wherein a transition of a clock edge of the output signal between first and second voltage levels is based at least in part on a bias signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.