Anneal to minimize leakage current in DRAM capacitor

US8647960B2 · kind B2 · utility

Assignees

• INTERMOLECULAR, INC. · US
• ELPIDA MEMORY, INC. · JP

Inventors

• Wim Deweerd · San Jose, US
• Hiroyuki Ode · Kure, JP

Key dates

• Filing date: Nov 14, 2011
• Grant date: Feb 11, 2014
• Expiry date: Nov 14, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/692

Abstract

A method for forming a DRAM MIM capacitor stack comprises forming a first electrode layer, annealing the first electrode layer, forming a dielectric layer on the first electrode layer, annealing the dielectric layer, forming a second electrode layer on the dielectric layer, annealing the second electrode layer, patterning the capacitor stack, and annealing the capacitor stack for times greater than about 10 minutes, and advantageously greater than about 1 hour, at low temperatures (less than about 300 C) in an atmosphere containing less than about 25% oxygen and preferably less than about 10% oxygen.