Memory device and method of fabricating the same
US8647988B2 · kind B2 · utility
0Cited by
4References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2013 |
| Grant date | Feb 11, 2014 |
| Priority date | — |
| Expiry date | Mar 4, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.