Method for molding semiconductor device
US8652384B2 · kind B2 · utility
0Cited by
5References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2012 |
| Grant date | Feb 18, 2014 |
| Priority date | — |
| Expiry date | Jun 6, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus for molding a semiconductor device includes an upper mold chase and a lower mold chase. The mold chases are capable of being aligned with each other, forming spaced cavities for receiving a lead frame array that includes semiconductor dies for encapsulation. The cavities are aligned in spaced, vertical columns and gates are provided at the opening of each column of cavities. A molding compound is passed through the gates and flows uninterrupted through each cavity and encapsulates the semiconductor dies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.