Integration of non-noble DRAM electrode
US8652927B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2013 |
| Grant date | Feb 18, 2014 |
| Priority date | — |
| Expiry date | Jan 10, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
Abstract
A method for forming a capacitor stack is described. In some embodiments of the present invention, a first electrode structure is comprised of multiple materials. A first material is formed above the substrate. A portion of the first material is etched. A second material is formed above the first material. A portion of the second material is etched. Optionally, the first electrode structure receives an anneal treatment. A dielectric material is formed above the first electrode structure. Optionally, the dielectric material receives an anneal treatment. A second electrode material is formed above the dielectric material. Typically, the capacitor stack receives an anneal treatment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.