Wafer dicing employing edge region underfill removal
US8652941B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 17, 2012 |
| Grant date | Feb 18, 2014 |
| Priority date | — |
| Expiry date | May 17, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/12042
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a dielectric material layer embedding metal structures is ablated from the chip-containing substrate by laser grooving, which is performed on dicing channels of the chip-containing substrate. Subsequently, an underfill layer is formed over the dielectric material layer in a pattern that excludes the peripheral areas of the chip-containing substrate. The physically exposed dicing channels at the periphery can be employed to align a blade to dice the chip-containing substrate. In another embodiment, an underfill layer is formed prior to any laser grooving. Mechanical cutting of the underfill layer from above dicing channels is followed by laser ablation of the dicing channels and subsequent mechanical cutting to dice a chip-containing substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.