Isolation structure, non-volatile memory having the same, and method of fabricating the same
US8653592B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2011 |
| Grant date | Feb 18, 2014 |
| Priority date | — |
| Expiry date | Jan 16, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76205
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an isolation structure, comprising: (a) providing a base having a recess; (b) forming a stop layer on the base and in the recess; (c) forming a dielectric material on the stop layer so as to allow the rest of the recess to be filled with the dielectric material; (d) removing the dielectric material over the base by performing a chemical mechanical polishing (CMP) process until a part of the stop layer is exposed so as to form a dielectric layer in the recess; and (e) removing a part of the stop layer, wherein the another part of the stop layer and the dielectric layer filled in the recess constitute the isolation structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.