Electronic component package fabrication method and structure
US8653674B1 · kind B1 · utility
20Cited by
165References
20Claims
0Family size
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Key dates
| Filing date | Sep 15, 2011 |
| Grant date | Feb 18, 2014 |
| Priority date | — |
| Expiry date | Jan 5, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A redistribution pattern is formed on active surfaces of electronic components while still in wafer form. The redistribution pattern routes bond pads of the electronic components to redistribution pattern terminals on the active surfaces of the electronic components. The bond pads are routed to the redistribution pattern terminals while still in wafer form, which is a low cost and high throughput process, i.e., very efficient process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.