Read methods, circuits and systems for memory devices

US8654561B1 · kind B1 · utility

Assignee

• Adesto Technologies Corporation · US

Inventors

• John Ross Jameson · Burlingame, US
• John Dinh · Dublin, US
• Derric Lewis · Sunnyvale, US
• Daniel Wang · Redwood City, US
• Shane Hollmer · Grass Valley, US
• Nad Edward Gilbert · Gilbert, US
• Janet Wang · Los Altos, US

Key dates

• Filing date: Oct 19, 2011
• Grant date: Feb 18, 2014
• Expiry date: Oct 19, 2031

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C13/0061
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A memory device can include a plurality of programmable elements; at least one sense circuit that generates sense data values from detected impedances of accessed programmable elements; and at least one data store circuit that stores initial data values from the at least one sense circuit, and stores output data values from the at least one sense circuit after check conditions have been applied to at least one programmable element. The check conditions can induce a change in impedance for programmable elements programmed to at least one predetermined state. Methods can include reading data from at least one memory cell of a memory device comprising a plurality of such memory cells; if the read data has a first value, providing such data as an output value; and if the read data has a second value, repeating access to the memory cell to confirm the read data value.