Static random access memory cell with single-sided buffer and asymmetric construction
US8654562B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 2012 |
| Grant date | Feb 18, 2014 |
| Priority date | — |
| Expiry date | Aug 25, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Balanced electrical performance in a static random access memory (SRAM) cell with an asymmetric context such as a buffer circuit. Each memory cell includes a circuit feature, such as a read buffer, that has larger transistor sizes and features than the other transistors within the cell, and in which the feature asymmetrical influences the smaller cell transistors. For best performance, pairs of cell transistors are to be electrically matched with one another. One or more of the cell transistors nearer to the asymmetric feature are constructed differently, for example with different channel width, channel length, or net channel dopant concentration, to compensate for the proximity effects of the asymmetric feature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.