Sequential clock gating using net activity and XOR technique on semiconductor designs including already gated pipeline design
US8656326B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2013 |
| Grant date | Feb 18, 2014 |
| Priority date | — |
| Expiry date | Feb 13, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The circuit design process requires ways to reduce the power consumption of large integrated circuits and system-on-chip designs. This is typically done by introducing a process of clock gating thereby enabling or disabling flip-flops associated with specific functional blocks within the circuit. However, such changes in the circuit require synthesis and verification to ensure correctness of design and operation as sequential clock gating changes the state function dynamically. It is therefore necessary to define synthesis methods adapted to such dynamic changes in the design. According to an embodiment a sequential clock gating method uses an exclusive-OR technique to overcome the deficiencies of the prior art methods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.