Three dimensional NAND device and method of charge trap layer separation and floating gate formation in the NAND device
US8658499B2 · kind B2 · utility
137Cited by
13References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2012 |
| Grant date | Feb 25, 2014 |
| Priority date | — |
| Expiry date | Jul 9, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A monolithic three dimensional NAND string includes a vertical semiconductor channel and a plurality of control gate electrodes in different device levels. The string also includes a blocking dielectric layer, a charge storage region and a tunnel dielectric. A first control gate electrode is separated from a second control gate electrode by an air gap located between the major surfaces of the first and second control gate electrodes and/or the charge storage region includes silicide nanoparticles embedded in a charge storage dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.