Techniques for metal gate work function engineering to enable multiple threshold voltage nanowire FET devices
US8658518B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2012 |
| Grant date | Feb 25, 2014 |
| Priority date | — |
| Expiry date | Aug 17, 2032 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB82Y40/00
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method of fabricating a nanowire FET device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are etched in the SOI layer. The nanowires are suspended over the BOX. An interfacial oxide is formed surrounding each of the nanowires. A conformal gate dielectric is deposited on the interfacial oxide. A conformal first gate material is deposited on the conformal gate dielectric. A work function setting material is deposited on the conformal first gate material. A second gate material is deposited on the work function setting material to form at least one gate stack over the nanowires. A volume of the conformal first gate material and/or a volume of the work function setting material in the gate stack are/is proportional to a pitch of the nanowires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.