Transistor device and method for manufacturing the same
US8659079B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2012 |
| Grant date | Feb 25, 2014 |
| Priority date | — |
| Expiry date | May 29, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
Abstract
Provided is a transistor device including at least a vertical transistor structure. The vertical transistor structure includes a substrate, a dielectric layer, a gate, a first doped region, a second doped region, a third doped region, and a fourth doped region. The dielectric layer is disposed in a trench of the substrate. The gate is disposed in the dielectric layer. The gate defines, at both sides thereof, a first channel region and a second channel region in the substrate. The first doped region and the third doped region are disposed in the substrate and located below the first channel region and the second channel region, respectively. The second doped region and the fourth doped region are disposed in the substrate and located above the first channel region and the second channel region, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.