Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
US8659139B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2012 |
| Grant date | Feb 25, 2014 |
| Priority date | — |
| Expiry date | Apr 4, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic assembly can include a circuit panel having first and second panel contacts at respective first and second surfaces thereof, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. Each package can include a microelectronic element having a face and contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The terminals can include first terminals at positions within first and second parallel grids. The first terminals can be configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first grid can be a mirror image of signal assignments of the first terminals in the second grid.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.