Stub minimization for wirebond assemblies without windows
US8659143B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2012 |
| Grant date | Feb 25, 2014 |
| Priority date | — |
| Expiry date | Apr 5, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic package can include a substrate and a microelectronic element having a rear face facing a first surface of the substrate, a front face, and a column of element contacts extending in a first direction. The microelectronic element can include stacked electrically interconnected semiconductor chips. Edges of the microelectronic element can define an axial plane extending in the first direction and a third direction normal to the rear face. The package can include columns of terminals extending in the first direction at a second surface of the substrate. The terminals can include first terminals exposed in a central region of the second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location. The central region may have a width not more than 3.5 times a minimum pitch between adjacent terminal columns. The axial plane can intersect the central region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.