Patent · US Active

Method and system for performing self-tests in an electronic system

US8659310B2 · kind B2 · utility

2Cited by
5References
20Claims
0Family size

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Inventors

Key dates

Filing dateApr 15, 2011
Grant dateFeb 25, 2014
Priority date
Expiry dateAug 8, 2032

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/3004
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

A method and system for performing a self-test of power supply quality for an integrated circuit chip within an electronic system. The electronic system is subjected to a well-defined repetitive activity, such as by using an amplitude modulated system clock tree. With the repetitive activity causing current consumption within the chip, time-domain local power supply voltage (U(t)) is measured for a location on the chip. A set of time-domain measured voltage data (U(t)) is accumulated and transformed into the frequency domain to yield a local voltage profile (U(f)). The local voltage profile (U(f)) is compared with a reference voltage profile (U0(f)) to verify whether power supply quality at the chip location under test is adequate. Alternatively, a local impedance profile Z(f) evaluated from the local voltage profile (U(f)) may be compared to a reference impedance profile Z0(f).

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.