Error detection in high-speed asymmetric interfaces
US8661300B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2011 |
| Grant date | Feb 25, 2014 |
| Priority date | — |
| Expiry date | Jun 27, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component controls many operations of the second component, including receiving a signature from the second component over an existing line of the interface. The signature received is compared to a signature stored by the first component. Both signatures correspond to a transaction over the interface. Based on the comparison, the first component determines whether the transaction was successful, and directs the second component as necessary.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.