Patent · US Active

Combined silicon oxide etch and contamination removal process

US8664012B2 · kind B2 · utility

1Cited by

5References

19Claims

0Family size

Assignee

TOKYO ELECTRON LIMITED · JP

Inventors

Richard H. Gaylord · Saratoga Springs, US
Blaze Messer · Albany, US
Kaushik A. Kumar · Heverlee, BE

Key dates

Filing date	Sep 30, 2011
Grant date	Mar 4, 2014
Priority date	—
Expiry date	Dec 16, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method of forming a semiconductor device. A substrate having first and second materials is provided, wherein the second material is occluded by the first material. The substrate is etched using a first non-plasma etch process that etches the first material at a higher rate relative to a rate of etching the second material. The first non-plasma etch process exposes the second material that is overlying at least a portion of the first material. The second material is then etched using a plasma containing a reactive gas, which exposes the at least a portion of the first material. The first material including the at least a portion of the first material that was exposed by etching the second material are etched using a second non-plasma etch process.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.